Embodiments of the invention relate to voltage level shifter circuits.
Semiconductor memory devices are widely used, a typical example of which is an electrically erasable programmable read-only memory (EEPROM) that can perform write/read/erase operations using different control voltages. Such a memory device has three voltage terminals CG, RBL and TG for data write/read/erase operations, and is connected to a control circuit that transfers control signals to the voltage terminals. To this end, a voltage level shifter circuit is used to receive the control signals from the control circuit, to selectively shift the voltage of the control signal into a high-voltage level, and to transfer the same to the memory device.
FIG. 1 is a circuit diagram of a voltage level shifter circuit 10.
Referring to FIG. 1, the voltage level shifter circuit 10 includes a power voltage terminal VPP to which a power voltage is applied; an output terminal OUT for transferring an output signal to the outside; an enable terminal ENb; and four transistors 11, 12, 13 and 14 for controlling the voltage of the output signal.
The sources of the first and second transistors 11 and 12 are connected to the power voltage terminal VPP, and the gate of the first transistor 11 is connected to the drain of the second transistor 12. Also, the gate of the second transistor 12 is connected to the drain of the first transistor 11 to form a coupling circuit, and the drain of the second transistor 12 is connected to the output terminal OUT and the drain of the fourth transistor 14.
The drain of the first transistor 11 is connected to the drain of the third transistor 13, and the sources of the third and fourth transistors 13 and 14 are connected to a ground terminal. The gate of the third transistor 13 is connected to the enable terminal ENb and the gate of the fourth transistor 14, and an inverter 15 is connected between the gate of the third transistor 13 and the gate of the fourth transistor 14.
The first and second transistors 11 and 12 are PMOS transistors, and the third and fourth transistors 13 and 14 are NMOS transistors.
The voltage level shifter circuit 10 operates as follows.
First, when a low-voltage (VSS) signal is input to the enable terminal ENb, the low-voltage signal is applied to the gate of the third transistor 13 to turn off the third transistor 13. Also, the low-voltage signal applied to the enable terminal ENb is inverted by the inverter 15 into a high-voltage (VDD) signal, and the high-voltage signal is input to the gate of the fourth transistor 14. Thus, the fourth transistor 14 is turned on, and a low-voltage signal is transferred through the fourth transistor 14 to the output terminal OUT. At this point, the low-voltage signal transferred to the output terminal OUT is also input to the gate of the first transistor 11 connected to the output terminal OUT, and the first transistor 11 is turned on. Thus, a high-voltage signal is input to the gate of the second transistor 12 connected to the drain of the first transistor 11. When the high-voltage signal is input to the gate, the second transistor 12 is turned off.
Second, when a high-voltage signal is input to the enable terminal ENb, a high-voltage signal is applied to the gate of the third transistor 130 to turn on the third transistor 13. When the third transistor 13 is turned on, a low-voltage signal is input to the gate of the second transistor 12 connected to the drain of the third transistor 13. Thus, the second transistor 12 is turned on and a high-voltage signal (VPP) is applied to the output terminal OUT connected to the drain of the second transistor 12. Also, the high-voltage signal is input to the gate of the first transistor 11 which is connected to the output terminal OUT, and the first transistor 11 is turned off. Thus, the high-voltage signal applied to the enable terminal ENb is inverted by the inverter 15 into a low-voltage signal, and the fourth transistor 14 is turned off.
However, an enable signal of a lower voltage level is used according to the trend of the low power and the high integration of a semiconductor device. In this case, even when a high-voltage enable signal is applied, because its voltage level is relatively low, it can be difficult to satisfy a threshold voltage that enables a turn-on operation of a transistor.
For example, if an enable signal of about 5 V is compared with an enable signal of about 1.5 V, when 1.5 V signal is input to the enable terminal ENb, the third transistor 13 (that is, an NMOS transistor) may fail to properly turn on.
FIG. 2 is a simulation graph of signals of the voltage level shifter circuit 10 when an enable signal a2 of a high level (about 5 V) is applied thereto. FIG. 3 is a simulation graph of signals of the voltage level shifter circuit 10 when an enable signal c2 of a relatively low level (about 1.5 V) is applied thereto.
In the graphs of FIGS. 2 and 3, the X (horizontal) axis represents a time axis and the Y (vertical) axis represents a voltage axis. Also, from the tops of FIGS. 2 and 3, the first graphs (a1 and c1) represent power voltage signals, the second graphs (a2 and c2) represent enable signals, the third graphs (b1 and d1) represent drain signals of the first transistor 11, and the fourth graphs (b2 and d2) represent output signals.
Referring to FIG. 2, when an enable signal a2 of a high level (about 5 V) is applied, it can be seen that each signal is normally processed as described above. For example, if the enable signal a2 is of high voltage, a drain signal b1 of the first transistor 11 is of low voltage and an output signal b2 is of high voltage.
However, referring to FIG. 3, when an enable signal c2 of a relatively low level (about 1.5 V) is applied, the first transistor 11 does not necessarily operate normally. Thus, it can be seen that the voltage of the output signal d2 is not necessarily a desired value (e.g., it may be unstable and/or may not be controlled). This causes a degradation in the operational reliability of the voltage level shifter circuit 10.